By Michiel Steyaert, Arthur H.M. van Roermund, Johan Huijsing
Analog Circuit layout comprises the contribution of 18 tutorials of the 14th workshop on Advances in Analog Circuit layout. every one half discusses a selected todate subject on new and important layout rules within the sector of analog circuit layout. every one half is gifted via six specialists in that box and state-of-the-art details is shared and overviewed. This publication is quantity 14 during this winning sequence of Analog Circuit layout, delivering important details and perfect overviews of analog circuit layout, CAD and RF systems.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it appropriate to be used in a sophisticated layout course.
Read Online or Download Analog Circuit Design: RF Circuits: Wide band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage PDF
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Extra resources for Analog Circuit Design: RF Circuits: Wide band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage
It is ac-coupled using MIM capacitors to the amplifying transistors M1 and M2. Those transistors are operating in class-AB mode. They are respectively biased by nodes DC_N and DC_B, that themselves are determined by a bias current in a diode connected transistor. The bias currents provide on-chip automatic compensation for temperature and process variations. In this way, the variation of the gain over corners and temperature is very limited. The DC operating point is determined by the node DC_CM which is resistively connected to the drains of the amplifying transistors.
This gives rise to code dependencies. It is therefore imperative that the bulk of the charging is over before the end of one clock period. This switched operation clearly does not correspond to the normal operation of a cascode. Therefore it is important to not only have simulation results, which have often poor accuracy in strongly non-linear devices as DAC’s, but measurement results as well. 59 Fig. 13. Discharging of node N2. 6. Implementation and measurement results In  we have used the proposed structure with cascodes on top of the switches in a 10-bit binary-weighted DAC.
If the switch is switched on again then the initial conditions on node N2 are dependent on how long the switch has been turned off. This gives rise to code dependencies. It is therefore imperative that the bulk of the charging is over before the end of one clock period. This switched operation clearly does not correspond to the normal operation of a cascode. Therefore it is important to not only have simulation results, which have often poor accuracy in strongly non-linear devices as DAC’s, but measurement results as well.